Domino Logic Low Leakage Clock Keeper (LLCKDL) for Effective CMOS Logic Gates

Abstract

Propagation delay and power consumption are two critical challenges in deep-submicron CMOS VLSI semiconductor circuits. High leakage currents and increased noise sensitivity further exacerbate these issues, demanding innovative design techniques to enhance efficiency. This study presents a novel approach for designing CMOS logic gates using the Low Leakage Clock Keeper Domino Logic (LLCKDL). The proposed methodology aims to significantly reduce leakage power while improving noise immunity and operational efficiency. The LLCKDL technique incorporates an optimized clock-keeper circuit to minimize unnecessary power dissipation in dynamic logic while maintaining robust signal integrity. To validate its effectiveness, a 16-bit OR gate was designed and simulated using 45 nm CMOS GPDK technology in the Cadence environment. Comparative analysis with existing design methodologies demonstrates substantial improvements. Specifically, LLCKDL achieves an 86.36% reduction in average power consumption, a 56.93% decrease in propagation delay, and an 86.90% improvement in the energy-delay product (EDP). These results highlight the efficiency of LLCKDL in reducing power dissipation while ensuring high-speed operation, making it a promising design paradigm for next-generation low-power CMOS circuits. The proposed approach is particularly beneficial for high-performance VLSI applications, where both power efficiency and speed are crucial. By mitigating leakage power and enhancing noise resilience, LLCKDL offers a viable solution for improving the performance of deep-submicron CMOS logic circuits, paving the way for more energy-efficient and reliable semiconductor devices.