Optimized Decoder Design Using CNTFETs for SRAM Integration

Abstract

This study presents the structural analysis and operational performance of address decoder architectures based on Carbon Nanotube Field-Effect Transistors (CNTFETs), emphasizing the proposed Preceding Block Mirror (PBM) Decoder. As traditional MOSFET scaling reaches its limits, CNTFETs emerge as a compelling alternative, offering superior electrical characteristics. Efficient address decoding is critical in Static Random-Access Memory (SRAM) systems to enable high-speed and reliable data access.

Three distinct CNTFET-based decoder architectures—namely the Conventional AND Decoder, the Universal Block Decoder, and the novel PBM Decoder—are designed and evaluated using Cadence Virtuoso. Among these, the PBM Decoder demonstrates notable gains in performance by significantly reducing power usage and propagation delay. Simulation results validate its potential as a power-efficient and high-speed solution for future SRAM applications.