Performance Analysis of a Novel Multilevel Inverter with Reduced Number of Switches

Abstract

Multilevel inverters (MLI) are important and widely accepted under DC to AC converter family for medium and low power applications. In the paper a “new inverter topology” for multi-level is developed. The primary purpose of the work is to reduce the switch count number for considerable level of output voltage and also to reduce gate drives required. It also aims at analysis of performance of proposed topology of new multilevel inverter. Output of fifteen stages is generated from the proposed topology. For which only eight switching devices, four diode and three asymmetrical sources are used. Thus, the space and cost for installation is reduced. The designed topology is simulated with normal “pulse width modulation (PWM)” as well as “sinusoidal pulse width modulation (SPWM)”. Both the Simulation results are discussed with respect to “output voltage, current, Total Harmonic Distortion (THD)”. A comparative study is also made between the topology developed with few other latest MLI topologies.